K-micro And Anritsu Collaborate To Develop First Test Tool And Methodology To Analyze 10g Epon Chips

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8th December 2009, 05:32am - Views: 808





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MEDIA RELEASE PR37408


K-micro and Anritsu Collaborate to Develop First Test Tool and Methodology to Analyze

10G EPON Chips


SAN JOSE, Calif., Dec. 7 /PRNewswire-AsiaNet/ --


          Successful test of K-micro's CTXL1 10G EPON SerDes chip using

   Anritsu's Signal Quality Analyzer, MP1800A, paves the way for 10G EPON

                            systems to be shipped

    


    K-micro (Kawasaki Microelectronics America), a leader in advanced ASICs,

and Anritsu announced the development of the first test tool and methodology

to analyze 10Gbps Ethernet Passive Optical Network (EPON) chips. The

successful test of K-micro's CTXL1 10G EPON SerDes chip using Anritsu's

Signal Quality Analyzer, MP1800A, paves the way for 10G EPON systems to be

shipped.


    Precise measurements of K-micro's CTXL1 10G EPON SerDes chip demonstrate

its innovative burst mode lock time of '20nsec'. "We have worked with

Anritsu, a company well-respected for its technology test solutions, to

develop testing for EPON chips because our customers are ready to implement

EPON applications and need to know that the chips meet the specifications for

the products," said Vijay Pathak, CTO at K-micro.


    There are two major challenges to evaluate 10G EPON Optical Line

Termination (OLT) burst mode SerDes:


    1) A Bit Error Rate Test (BERT) must examine only the delimiter

       and the payload, and calculate bit error rate. The sync pattern 

       shouldn't be taken into account.

    2) SerDes must keep the same latency for every burst. Or, BERT must

       have the capability to allow latency difference between bursts.


    MP1800A's powerful Pulse Pattern Generator (PPG) and Error Detector (ED)

easily and accurately calculate the bit error rate, and CTXL1's unique Built

In Self Test (BIST) function can successfully align the latency on every

burst so BERT is not required to compensate for the variation of the latency

between bursts. These two cutting edge technologies met and made it possible

to measure burst mode lock time at 10.3125Gbps with BER of better than

1.0E-12.


    "Successfully testing K-micro's 10G EPON chip is an important step for the

EPON applications market," said Wade Hulon, Vice President and General

Manager, Americas Region at Anritsu. "The two companies worked side-by-side

to overcome the challenges of testing this type of technology so that it

could be made available to customers."


    About Anritsu

    Anritsu Company (www.us.anritsu.com) is the American subsidiary of

Anritsu Corporation, a global provider of innovative communications test and

measurement solutions for more than 110 years. Anritsu provides test

equipment for legacy and next-generation wired and wireless communication

systems. Anritsu products include wireless, optical, microwave/RF, and

digital instruments as well as operations support systems for R&D,

Science Information Technology K-micro 3 image

manufacturing, installation, and maintenance. Anritsu also provides precision

microwave/RF components, optical devices, and high-speed electrical devices

for communication products and systems. With offices throughout the world,

Anritsu sells in over 90 countries with approximately 4,000 employees.


    About K-micro (Kawasaki Microelectronics America)

    K-micro's innovative ASIC technologies and world-class design support are

used in the consumer electronics, computer, office-automation, networking and

storage markets. The company is an active participant in industry standards

organizations, including InterNational Committee for Information Technology

Standards (INCITS) Technical Committee T10 for SCSI Storage Interfaces, PCI

Special Interest Group (PCI-SIG), USB Implementers Forum, Universal Plug and

Play Forum (UPnP), the Digital Display Working Group (DDWG), Home Phoneline

Networking Alliance (HomePNA), International Telecommunication Union (ITU)

and OCP International Partnership (OCP-IP). K-micro has design centers in San

Jose, Taipei, and Tokyo. For more information, contact the company at

408-570-0555, or visit http://www.k-micro.us


     SOURCE: K-micro


    CONTACT: Sacha Arts of Slider & Associates

             +1-408-356-3099

             sacha@sliderassociates.com, for K-micro; or 


             Kim Collins of Americas Marketing

             +1-972-400-1865

             Kim.Collins@anritsu.com, for Anritsu




Translations:


   Korean (http://asianetnews.net/Download.asp?ID=142273)




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